diff --git a/MAINTAINERS b/MAINTAINERS
index 5471c1d..39743c7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -698,6 +698,7 @@
 
 	MS7750SE		SH7750
 	MS7722SE		SH7722
+	R2DPlus			SH7751R
 
 Mark Jonas <mark.jonas@de.bosch.com>
 
diff --git a/MAKEALL b/MAKEALL
index ea02a8a..756cf87 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -701,6 +701,7 @@
 	ms7722se	\
 	Migo-R		\
 	r7780mp		\
+	r2dplus		\
 "
 
 LIST_sh3="		\
diff --git a/Makefile b/Makefile
index f985045..420c684 100644
--- a/Makefile
+++ b/Makefile
@@ -2867,6 +2867,11 @@
 	@echo "#define CONFIG_R7780MP 1" >> include/config.h
 	@./mkconfig -a $(@:_config=) sh sh4 r7780mp
 
+r2dplus_config  :   unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_R2DPLUS 1" >> include/config.h
+	@./mkconfig -a $(@:_config=) sh sh4 r2dplus
+
 #########################################################################
 #########################################################################
 #########################################################################
diff --git a/board/r2dplus/Makefile b/board/r2dplus/Makefile
new file mode 100644
index 0000000..ed609ea
--- /dev/null
+++ b/board/r2dplus/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= r2dplus.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+	$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#################################################################
diff --git a/board/r2dplus/config.mk b/board/r2dplus/config.mk
new file mode 100644
index 0000000..1ec7dcc
--- /dev/null
+++ b/board/r2dplus/config.mk
@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+TEXT_BASE = 0x0FFC0000
diff --git a/board/r2dplus/lowlevel_init.S b/board/r2dplus/lowlevel_init.S
new file mode 100644
index 0000000..5755de8
--- /dev/null
+++ b/board/r2dplus/lowlevel_init.S
@@ -0,0 +1,154 @@
+/*
+ * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
+ * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
+ * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+
+	.global lowlevel_init
+	.text
+	.align  2
+
+lowlevel_init:
+
+	mov.l	CCR_A, r1
+	mov.l	CCR_D_D, r0
+	mov.l	r0,@r1
+
+	mov.l	MMUCR_A,r1
+	mov.l	MMUCR_D,r0
+	mov.w	r0,@r1
+
+	mov.l	BCR1_A,r1
+	mov.l	BCR1_D,r0
+	mov.l	r0,@r1
+
+	mov.l	BCR2_A,r1
+	mov.l	BCR2_D,r0
+	mov.w	r0,@r1
+
+	mov.l	BCR3_A,r1
+	mov.l	BCR3_D,r0
+	mov.w	r0,@r1
+
+	mov.l	BCR4_A,r1
+	mov.l	BCR4_D,r0
+	mov.l	r0,@r1
+
+	mov.l	WCR1_A,r1
+	mov.l	WCR1_D,r0
+	mov.l	r0,@r1
+
+	mov.l	WCR2_A,r1
+	mov.l	WCR2_D,r0
+	mov.l	r0,@r1
+
+	mov.l	WCR3_A,r1
+	mov.l	WCR3_D,r0
+	mov.l	r0,@r1
+
+	mov.l	PCR_A,r1
+	mov.l	PCR_D,r0
+	mov.w	r0,@r1
+
+	mov.l	LED_A,r1
+	mov	#0xff,r0
+	mov.w	r0,@r1
+
+	mov.l	MCR_A,r1
+	mov.l	MCR_D1,r0
+	mov.l	r0,@r1
+
+	mov.l	RTCNT_A,r1
+	mov.l	RTCNT_D,r0
+	mov.w	r0,@r1
+
+	mov.l	RTCOR_A,r1
+	mov.l	RTCOR_D,r0
+	mov.w	r0,@r1
+
+	mov.l	RFCR_A,r1
+	mov.l	RFCR_D,r0
+	mov.w	r0,@r1
+
+	mov.l	RTCSR_A,r1
+	mov.l	RTCSR_D,r0
+	mov.w	r0,@r1
+
+	mov.l	SDMR3_A,r1
+	mov	#0x55,r0
+	mov.b	r0,@r1
+
+	/* Wait DRAM refresh 30 times */
+	mov.l	RFCR_A,r1
+	mov	#30,r3
+1:
+	mov.w	@r1,r0
+	extu.w	r0,r2
+	cmp/hi	r3,r2
+	bf	1b
+
+	mov.l	MCR_A,r1
+	mov.l	MCR_D2,r0
+	mov.l	r0,@r1
+
+	mov.l	SDMR3_A,r1
+	mov	#0,r0
+	mov.b	r0,@r1
+
+	mov.l	IRLMASK_A,r1
+	mov.l	IRLMASK_D,r0
+	mov.l	r0,@r1
+
+	mov.l	CCR_A, r1
+	mov.l	CCR_D_E, r0
+	mov.l	r0, @r1
+
+	rts
+	nop
+
+	.align	2
+CCR_A:		.long	CCR		/* Cache Control Register */
+CCR_D_D:	.long	0x0808		/* Flush the cache, disable */
+CCR_D_E:	.long	0x8000090B
+
+FRQCR_A:	.long	FRQCR		/* FRQCR Address */
+FRQCR_D:	.long	0x00000e0a	/* 03/07/15 modify */
+BCR1_A:	.long	BCR1		/* BCR1 Address */
+BCR1_D:	.long	0x00180008
+BCR2_A:	.long	BCR2		/* BCR2 Address */
+BCR2_D:	.long   0xabe8
+BCR3_A:	.long	BCR3		/* BCR3 Address */
+BCR3_D:	.long	0x0000
+BCR4_A:	.long	BCR4		/* BCR4 Address */
+BCR4_D:	.long	0x00000010
+WCR1_A:	.long	WCR1		/* WCR1 Address */
+WCR1_D:	.long	0x33343333
+WCR2_A:	.long	WCR2		/* WCR2 Address */
+WCR2_D:	.long	0xcff86fbf
+WCR3_A:	.long	WCR3		/* WCR3 Address */
+WCR3_D:	.long	0x07777707
+LED_A:		.long	0x04000036	/* LED Address */
+RTCNT_A:	.long	RTCNT		/* RTCNT Address */
+RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
+RTCOR_A:	.long	RTCOR		/* RTCOR Address */
+RTCOR_D:	.long	0xA534		/* RTCOR Write Code  */
+RTCSR_A:	.long	RTCSR		/* RTCSR Address */
+RTCSR_D:	.long	0xA510		/* RTCSR Write Code */
+SDMR3_A:	.long   0xFF9400CC	/* SDMR3 Address */
+SDMR3_D:	.long	0x55
+MCR_A:		.long	MCR		/* MCR Address */
+MCR_D1:	.long	0x081901F4	/* MRSET:'0' */
+MCR_D2:	.long	0x481901F4	/* MRSET:'1' */
+RFCR_A:	.long	RFCR		/* RFCR Address */
+RFCR_D:	.long	0xA400		/* RFCR Write Code A4h Data 00h */
+PCR_A:		.long	PCR		/* PCR Address */
+PCR_D:		.long	0x0000
+MMUCR_A:	.long	MMUCR		/* MMUCCR Address */
+MMUCR_D:	.long	0x00000000	/* MMUCCR Data */
+IRLMASK_A:	.long	0xA4000000	/* IRLMASK Address */
+IRLMASK_D:	.long	0x00000000	/* IRLMASK Data */
diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c
new file mode 100644
index 0000000..2ee3ea2
--- /dev/null
+++ b/board/r2dplus/r2dplus.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <asm/processor.h>
+#include <asm/pci.h>
+
+int checkboard(void)
+{
+	puts("BOARD: Renesas Solutions R2D Plus\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+#define FPGA_BASE          0xA4000000
+#define FPGA_CFCTL         (FPGA_BASE + 0x04)
+#define FPGA_CFPOW         (FPGA_BASE + 0x06)
+#define FPGA_CFCDINTCLR    (FPGA_BASE + 0x2A)
+
+void ide_set_reset (int idereset)
+{
+	/* if reset = 1 IDE reset will be asserted */
+	if (idereset){
+		(*(vu_short *)FPGA_CFCTL) = 0x432;
+		(*(vu_short *)FPGA_CFPOW) |= 0x02;
+		(*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
+	}
+}
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+	pci_sh7751_init( &hose );
+}
+#endif /* CONFIG_PCI */
diff --git a/board/r2dplus/u-boot.lds b/board/r2dplus/u-boot.lds
new file mode 100644
index 0000000..96d8d81
--- /dev/null
+++ b/board/r2dplus/u-boot.lds
@@ -0,0 +1,105 @@
+/*
+ * Copyrigth (c) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	   Base address of internal SDRAM is 0x0C000000.
+	   Although size of SDRAM can be either 16 or 32 MBytes,
+	   we assume 16 MBytes (ie ignore upper half if the full
+	   32 MBytes is present).
+
+	   NOTE: This address must match with the definition of
+	   TEXT_BASE in config.mk (in this directory).
+
+	*/
+	. = 0x0C000000 + (64*1024*1024) - (256*1024);
+
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .);
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
new file mode 100644
index 0000000..c20baca
--- /dev/null
+++ b/include/configs/r2dplus.h
@@ -0,0 +1,150 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_SH		1
+#define CONFIG_SH4		1
+#define CONFIG_CPU_SH7751	1
+#define CONFIG_CPU_SH_TYPE_R	1
+#define CONFIG_R2DPLUS		1
+#define __LITTLE_ENDIAN__	1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+/* SCIF */
+#define CFG_SCIF_CONSOLE	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_CONS_SCIF1	1
+#define BOARD_LATE_INIT		1
+
+#define CONFIG_BOOTDELAY	-1
+#define CONFIG_BOOTARGS		"console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE	1
+
+/* Network setting */
+#define CONFIG_NETMASK		255.0.0.0
+#define CONFIG_IPADDR		10.0.192.51
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_GATEWAYIP	10.0.0.1
+
+/* SDRAM */
+#define CFG_SDRAM_BASE		(0x8C000000)
+#define CFG_SDRAM_SIZE		(0x04000000)
+
+#define CFG_LONGHELP
+#define CFG_PROMPT		"=> "
+#define CFG_CBSIZE		256
+#define CFG_PBSIZE		256
+#define CFG_MAXARGS		16
+#define CFG_BARGSIZE		512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_MEMTEST_START	(CFG_SDRAM_BASE)
+#define CFG_MEMTEST_END		(TEXT_BASE - 0x100000)
+
+#define CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 32 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE)
+#define CFG_MONITOR_LEN		(128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN		(256 * 1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE	(256)
+#define CFG_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/*
+ * NOR Flash
+ */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+
+#if defined(CONFIG_R2DPLUS_OLD)
+#define CFG_FLASH_BASE		(0xA0000000)
+#define CFG_MAX_FLASH_BANKS (1)	/* Max number of
+				 * Flash memory banks
+				 */
+#define CFG_MAX_FLASH_SECT  142
+#define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
+
+#else /* CONFIG_R2DPLUS_OLD */
+
+#define CFG_FLASH_BASE		(0xA0000000)
+#define CFG_FLASH_CFI_WIDTH	0x04	/* 32bit */
+#define CFG_MAX_FLASH_BANKS	(2)
+#define CFG_MAX_FLASH_SECT	270
+#define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE,\
+			CFG_FLASH_BASE + 0x100000,\
+			CFG_FLASH_BASE + 0x400000,\
+			CFG_FLASH_BASE + 0x700000, }
+#endif /* CONFIG_R2DPLUS_OLD */
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT	120000
+#define CFG_FLASH_WRITE_TOUT	500
+
+/*
+ * SuperH Clock setting
+ */
+#define CONFIG_SYS_CLK_FREQ	60000000
+#define TMU_CLK_DIVIDER		4
+#define CFG_HZ			(CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+#define	CFG_PLL_SETTLING_TIME	100/* in us */
+
+/*
+ * IDE support
+ */
+#define CONFIG_IDE_RESET	1
+#define CFG_PIO_MODE		1
+#define CFG_IDE_MAXBUS		1 /* IDE bus */
+#define CFG_IDE_MAXDEVICE	1
+#define CFG_ATA_BASE_ADDR	0xb4000000
+#define CFG_ATA_STRIDE		2 /* 1bit shift */
+#define CFG_ATA_DATA_OFFSET	0x1000	/* data reg offset */
+#define CFG_ATA_REG_OFFSET	0x1000	/* reg offset */
+#define CFG_ATA_ALT_OFFSET	0x800	/* alternate register offset */
+
+/*
+ * SuperH PCI Bridge Configration
+ */
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7751_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW	1
+#define __io
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
+#define CONFIG_PCI_IO_BUS	0xFE240000	/* IO space base address */
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x00040000	/* Size of IO window */
+
+/*
+ * Network device (RTL8139) support
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_RTL8139
+#define _IO_BASE		0x00000000
+#define KSEG1ADDR(x)		(x)
+
+#endif /* __CONFIG_H */